The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.
For example, it is desirable to decrease the effective channel length in a semiconductor device. The initial distance between the source-side junction and the drain-side junction of a semiconductor device is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. Decreasing the effective channel length reduces the distance between the depletion regions associated with the source and drain of a semiconductor device. As a result, less gate charge is required to invert the channel of a semiconductor device having a short effective channel length, resulting in faster switching speeds.